In recent years, a liquid crystal matrix display device, especially a so-called active matrix type liquid crystal display device provided with a switching element for each pixel, has been under research and development at various facilities for use as a thin picture image display device. An MIS-type TFT is generally used as the switching element.
FIG. 7 shows a known electric circuit diagram of an active matrix type liquid crystal display device.
In the gate wiring 2, for example, when Xi is selected, the TFT 21 connected thereto conducts, and picture image signals are transmitted to the picture element electrode 9 through the source wiring 13 and the TFT 21. To the liquid crystal layer 22 is applied the electric voltage difference between the pixel electrode 9 and the counter electrode 24 provided on the substrate counterposed thereto, putting the liquid crystal layer therebetween, and the optical transparency of the liquid crystal layer 22 is changed by this voltage difference and a display is produced. After the TFT 21 has been turned off, the voltage of the pixel electrode 9 is held until the same TFT 21 is selected for the next time, by the capacitance component of the liquid crystal layer 22 itself and the hold capacitance 23 between the picture element electrode 9 and the Xi-l in the gate wiring 2. The hold capacitance 23 is provided since the voltage of the pixel electrode 9 is lowered by leakage current in the period when the TFT 21 is turned off when only the capacitance of the liquid crystal layer 22 is provided.
In FIGS. 8 to 10 further illustrating the prior art, numeral 1 denotes an insulating substrate, 2 a gate wiring, 3 a gate insulating layer, 4 an amorphous silicon layer, 5 a protective insulating layer, 7 an n-type silicon layer provided for the ohmic contact, 8 a metal layer, 9 a pixel electrode, 10 a source electrode, 11 a drain electrode, 12 a gate electrode, and 13 a source wiring. As can be seen in FIGS. 8 and 10 the hold capacitance is formed between the gate wiring 2 and the pixel electrode 9 by putting the gate insulating layer 3, the amorphous silicon layer 4 and the protective insulating layer 5 therebetween.
In FIG. 9, the thickness of the amorphous silicon layer 4 is about 50 nm, and the thickness of the protective insulating layer 5 is about 400 nm, and when both thickness are totaled, a thickness of about 450 nm is obtained. The ITO exclusively used as the pixel electrode 9 renders it difficult to cover a step difference of 450 nm well, and produces cutting in step 9a, and as a result, a defect occurs since the hold capacitance was electrically separated from the pixel electrode.